It is sometimes desirable to perform signal processing using continuous-valued discrete-time samples of an input signal. This may be advantageous in some applications where high operating speed is important, and where the repeatability offered by digital signal processing is not required. In such an application it may be possible to perform the processing with less complex hardware and power consumption than a digital implementation would require.
One type of signal processing which is frequently necessary with discrete-time signals is sampling rate conversion. For example, sampling rate conversion can be used to interface to a communications system or a data storage system that uses a different sampling rate. Sampling rate conversion also can be used when partitioning a signal into sub-bands for sub-band processing.
The principal techniques to accomplish sampling rate conversion are referred to as interpolation and decimation. In interpolation, a discrete-time signal is up-sampled and lowpass filtered to generate a higher sample rate signal. In decimation, a discrete-time signal is lowpass filtered and down-sampled to generate a lower sample rate signal. One example circuit for carrying out interpolation and decimation with digital signals is described in U.S. Pat. No. 4,020,332, which is incorporated herein by reference. A more recent and complete treatment of the subject is found in "Multirate Digital Signal Processing by Crochiere and Rabiner", Prentice-Hall, copyright 1983, which is also incorporated herein by reference.
One example of a technique for processing continuous-valued discrete-time samples of an input signal is shown in U.S. Pat. No. 5,396,446, which is incorporated herein by reference. That patent discloses a circuit which filters an analog input signal with digital filter coefficients. The filter circuit includes a bank of N sample-and-hold devices which are activated cyclically to sample and store an analog input signal at N most recent sample times. The cyclic activation of the sample-and-hold devices (in a manner essentially equivalent to a circular-buffer) avoids the use of an analog shift-register, and so avoids the accumulation of errors associated with transferring continuous-valued samples from one sample-and-hold device to another. The digital filter coefficients are stored in a filter-coefficient shift-register, where each cell of the shift-register holds a digital value representing a filter coefficient. The shift-register contents are cycled at the input sample rate in order to maintain the correct correspondence of the N filter coefficients with the circularly buffered input samples. A multiplication circuit that employs N multipliers, each capable of multiplying a continuous-valued input sample by a digital value, connects the filter-coefficient shift-register and the sample-and-hold devices. The N multiplier outputs are summed to generate a filtered continuous-valued discrete-time signal. The input and output sample rates of the device are the same. U.S. Pat. No. 5,563,819 to Nelson discloses another similar system for processing continuous-valued discrete-time samples of an input signal.
Due to the need sometimes to change the sample rate, and because it sometimes is desirable to carry out the processing using continuous-valued discrete-time samples, it is an object of the present invention to provide a signal processor which can perform sampling rate conversion of continuous-valued discrete-time samples. More particularly, it would be desirable to provide an signal processor with the basic function of interpolation and decimation of such samples. It is also an object of the present invention to provide a interpolator/decimator configuration which is relatively simple to implement. Another object of the invention is to provide an interpolator/decimator which does not introduce significant artifacts into the signal.